Adding hardware to a course in Computer Design and Architecture has a number of challenges. These challenges include already crammed computer science curricula, costs associated with the hardware and a lack of interest among some computer science students. Presented here is an approach to overcome these challenges by carefully selecting the hardware used and providing the proper amount of scaffolding. By doing so, it is possible to successfully incorporate economy hardware into a single semester course on Computer Design and Architecture targeted for computer science students. In particular, the approach makes use of and extends students’ prior knowledge of HDL through a HDL-to-VHDL syntax translator. This eases the process of designing synthesizable circuits which can be implemented on field programmable gate arrays. In addition to the syntax translator; several tutorials, videos and on-line resources have been developed to aid students through the construction of their own designs. These resources allow students to implement their own projects with limited guidance. Sample student projects include a 7-segment display decoder and simple arithmetic unit.
HDL to VHDL Translator:
Incorporating Economy Hardware into a Computer Design and Architecture Course by Jason Litchfield, Steven Ledsworth, and Jesse Eickholt is licensed under a Creative Commons Attribution 4.0 International License .